is an abbreviation for "Double Data Rate". DDR is indeed very similar to the normal Synchronous DRAM. The normal Synchronous DRAM (we now called SDR) was evolved out of the standard DRAM.
The standard DRAM
receives its address command in two address words. It is a multiplex scheme to save input pins. The first address word is latched into the DRAM chip with the Row Address Strobe (RAS). Following the RAS command is the Column Address Strobe (CAS) for latching the second address word. Shortly after the Ras and Cas strobes, the stored data is valid for reading.
The SDR DRAM
combines a clock with the standard DRAM. The Ras, Cas, and also Data valid are enabled on the rising edge of each clock cycle. Due to the clocking, the position of the data and the rest of the signals are now very predictable. Thus that data latch strobes can be positioned very precisely. Since the data valid window is very predictable, the memory can now be divided into four banks to allow internal cell pre-charge and pre-fetch. Burst mode is also added to allow consecutive address fetching without repeating the Ras strobe. Continuous Cas strobe would bring out consecutive data as long as they are from the same Row.
works very similar to the SDR except that data is read at both leading edge and falling edge of the clock. Thus a single frequency clock can result in a data transfer as fast as twice the frequency of the clock. The new generation of DDR memory is running at 2