popopot
04-13-2007, 04:41 PM
From: http://www.physorg.com/news95575580.html
IBM today announced a breakthrough chip-stacking technology in a manufacturing environment that paves the way for three-dimensional chips that will extend Moore’s Law beyond its expected limits. The technology – called “through-silicon vias” -- allows different chip components to be packaged much closer together for faster, smaller, and lower-power systems.
The IBM breakthrough enables the move from horizontal 2-D chip layouts to 3-D chip stacking, which takes chips and memory devices that traditionally sit side by side on a silicon wafer and stacks them together on top of one another. The result is a compact sandwich of components that dramatically reduces the size of the overall chip package and boosts the speed at which data flows among the functions on the chip.
“This breakthrough is a result of more than a decade of pioneering research at IBM,” said Lisa Su, vice president, Semiconductor Research and Development Center, IBM. “This allows us to move 3-D chips from the 'lab to the fab' across a range of applications.”
The new IBM method eliminates the need for long-metal wires that connect today’s 2-D chips together, instead relying on through-silicon vias, which are essentially vertical connections etched through the silicon wafer and filled with metal. These vias allow multiple chips to be stacked together, allowing greater amounts of information to be passed between the chips.
The technique shortens the distance information on a chip needs to travel by 1000 times, and allows for the addition of up to 100 times more channels, or pathways, for that information to flow compared to 2-D chips.
More at the link above.
IBM today announced a breakthrough chip-stacking technology in a manufacturing environment that paves the way for three-dimensional chips that will extend Moore’s Law beyond its expected limits. The technology – called “through-silicon vias” -- allows different chip components to be packaged much closer together for faster, smaller, and lower-power systems.
The IBM breakthrough enables the move from horizontal 2-D chip layouts to 3-D chip stacking, which takes chips and memory devices that traditionally sit side by side on a silicon wafer and stacks them together on top of one another. The result is a compact sandwich of components that dramatically reduces the size of the overall chip package and boosts the speed at which data flows among the functions on the chip.
“This breakthrough is a result of more than a decade of pioneering research at IBM,” said Lisa Su, vice president, Semiconductor Research and Development Center, IBM. “This allows us to move 3-D chips from the 'lab to the fab' across a range of applications.”
The new IBM method eliminates the need for long-metal wires that connect today’s 2-D chips together, instead relying on through-silicon vias, which are essentially vertical connections etched through the silicon wafer and filled with metal. These vias allow multiple chips to be stacked together, allowing greater amounts of information to be passed between the chips.
The technique shortens the distance information on a chip needs to travel by 1000 times, and allows for the addition of up to 100 times more channels, or pathways, for that information to flow compared to 2-D chips.
More at the link above.